004
26.10.2025, 09:39 Uhr
Bea
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cpu z80
CTC0 equ 10h
CTC1 equ 11h
CTC2 equ 12h
CTC3 equ 13h
SIO_DATA_A equ 18h ; address of SIO A/D
SIO_CTRL_A equ 19h ; address of SIO A/C
SIO_DATA_B equ 1Ah ; address of SIO B/D
SIO_CTRL_B equ 1Bh ; address of SIO B/C
CLK equ 2764800 ; clock in Hz
org 2000h
ld a,00000111b ; init ctc Fosc/16
out (CTC0),a
ld a,9 ; divider /9
out (CTC0),a
ld a, 00011000b ; store channel reset command in a
out (SIO_CTRL_A),a ; send it to channel a
ld a, 00000100b ; select WR4
out (SIO_CTRL_A),a
ld a, 01000100b ; 16x clock, 1 stop bit, no parity
out (SIO_CTRL_A),a
ld a, 00000011b ; select WR3
out (SIO_CTRL_A),a
ld a, 11000000b ; 8 bits
out (SIO_CTRL_A),a
ld a, 00000101b ; select WR5
out (SIO_CTRL_A),a
ld a, 01100000b ; DTR inactive, 8 bits
out (SIO_CTRL_A),a
ld a, 00000101b ; select WR5
out (SIO_CTRL_A),a
ld a, 01101000b ; enable tx
out (SIO_CTRL_A),a
wait ld a, 00000000b ; select RR0
out (SIO_CTRL_A), a ; send the pointer
in a, (SIO_CTRL_A) ; read byte from RR0
bit 2, a ; test for the tx buffer being empty
jr z, wait ; loop until buffer becomes empty
ld a, 'U'
out (SIO_DATA_A),a ; send the character to the SIO
ld bc,0
delay dec bc
ld a,b
or c
jr nz,delay
jr wait
end
Dieser Beitrag wurde am 26.10.2025 um 09:41 Uhr von Bea editiert. |
